The present invention generally relates to a semiconductor memory device utilizing the polarization of a ferroelectric, particularly to a reference potential generation circuit for use in a ferroelectric memory circuit in order to determine a data state of a memory cell formed of a single transistor and a single ferroelectric capacitor.
A semiconductor memory device using a ferroelectric capacitor is a memory device utilizing the spontaneous polarization property of a ferroelectric used as a capacitive dielectric of a capacitor. On this account, it has characteristics that the refresh operation is unnecessary, which is needed for DRAM (Dynamic Random Access Memory) being a traditional semiconductor memory device, and data stored in memory cells is not lost irrespective of the state of a power source.
For the memory cell using the ferroelectric, there are those formed of a single MOS (Metal Oxide Semiconductor) transistor and a single ferroelectric capacitor (1T/1C) which is traditionally adopted in DRAM and those formed of two MOS transistors and two ferroelectric capacitors (2T/2C). Particularly, from increasing demands of downsizing and greater integration of semiconductor devices in recent years, attention is focused on the memory cell of the 1T1C structure in these memory cell configurations.
However, in the case of the semiconductor memory device using the ferroelectric memory cell of the 1T/1C structure, the space required for each memory cell is reduced to be suitable for greater integration, but the reference potential for amplifying the signals of the memory cells is needed when data stored in the memory cells is read out. More specifically, a reference potential generation circuit for generating the reference potential is required.
As a traditional reference generation circuit, it is described in JP-A-8-115596, for example.
FIG. 7 depicts a traditional example. The reference generation circuit is configured of bit lines BL and complementary bit lines BLb, both to be paired, reference cells RMC0 to RMC3 connected to each of the bit lines BL or the complementary bit lines BLb, reference word lines RWL, and a reference plate line RPL.
These reference cells RMC0 to RMC3 are disposed at the intersection of each of the bit lines and the reference word lines.
Among the reference cells RMC0 to RMC3, the reference cells RMC0 and RMC2 are connected to bit lines BL0 and BL1, which are configured of select transistors RT0 and RT2 operated by a reference word line RWL1 and ferroelectric capacitors H0 and H2 that one terminals are connected to the select transistors RT0 and RT2 and the others are connected to the reference plate line RPL. In addition, the reference cells RMC1 and RMC3 are connected to complementary bit lines BLb0 and BLb1, which are configured of select transistors RT1 and RT3 operated by a reference word line RWL0 and ferroelectric capacitors H1 and H3 that one terminals are connected to select transistors RT1 and RT3 and the others are connected to the reference plate line RPL.
Furthermore, a switching transistor T4 is connected between the two bit lines BL to which the reference cells RMC1 and RMC3 are connected, and a switching transistor T5 is connected between the two complementary bit lines BLb to which the reference cells RMC0 and RMC2 are connected. The switching transistors T4 and T5 are operated by a bit line equalizer signal EQ0 or EQ1.
The semiconductor memory device having the traditional 1T/1C structure has a reference control circuit for generating control signals for the reference potential generation circuit, word lines WL0 and WL1 and plate lines PL in addition to the reference potential generation circuit described above, and is configured of a sense amplifier circuit SA connected between one line of the bit lines BL or complementary bit lines BLb to which the reference cells RMC0 to RMC3 are connected and one line of the bit lines BL or complementary bit lines BLb to which memory cells MC0 to MC3 are connected, the sense amplifier circuit SA compares the potential generated in each of the bit lines and amplifies the signals of the memory cell.
Next, the readout operation in the semiconductor memory device having the traditional 1T/1C structure will be described. Here, the operation to read the data out of the MC0 into which Data 1 is written will be described, for example, where first data (Data 1) is set to power source potential Vdd and second data (Data 0) is set to ground potential Vss.
When the data of the MC0 connected to the bit line BL0 is read out, Data 1 is written into the complementary bit line BLb0 to which the potential reference potential is applied and into the reference cell connected to the BLb1 through the BLb0 and the switching transistor T4, the RMC1, for example, and Data 0 is written into the other RMC3 beforehand.
First, when a memory cell block including the MC0 is selected, a block select signal becomes active, and then the reference control circuit is activated by receiving the block select signal.
Subsequently, when the word line WL0 is activated and then the plate line PL0 is activated, the memory cell MC0 connected to these lines is selected, and the charge corresponding to the data written in the MC0 is carried to the BL0. At the same time, the reference word line RWL0 and the reference plate line RPL are activated, and the charge corresponding to Data 1 written in the RMC1 connected to these lines is carried to the BLb0, and the charge corresponding to Data 0 written in the RMC3 is carried to the BLb1.
After that, the bit line equalizer signal EQ0 is activated to operate switching transistor T4, and then the BLb0 is connected to the BLb1. More specifically, the BLb0 and BLb1 are short-circuited. At this time, the potential of each of the complementary bit lines BLb0 and BLb1 is turned to the intermediate potential of the potential held by each of the complementary bit lines before the short circuit because the capacitances held by the BLb0 and BLb1 are nearly the same. The intermediate potential becomes the reference potential used when data is read out of the memory cell MC0.
In this manner, after the reference potential is generated in the BLb0, the reference control circuit turns the EQ0 inactive to separate the BLb0 from the BLb1. At the same time, a sense amplifier circuit SA000 is activated, and the potential corresponding to Data 1 stored in the MC0 that is amplified by the SA000 and shown in the BL0 and the reference potential shown in the BLb0 are outputted to a digit line DB and complementary digit bit line DBb as data.